FIG. 1 is simplified schematic diagram showing a four transistor (4T) CMOS image sensor pixel including a fully pinned photodiode PPD and a transfer gate MX, which represents one embodiment of an IC including a deep implant.
Fully pinned diode PPD is a diode with finite and relatively small free charge capacity. In most cases the diode is constructed in p-type epi using deep n-type implant and additional shallow p+ implant above the deep n implant, the free charge of the pinned PD are electrons which accumulating in the potential well which is imposed by the implants. Evacuating electrons from this potential well through the transfer gate MX increases the voltage which is built on the diode. When all electrons are evacuated, the voltage reaches its highest value—VPINN. The integration of light can be started at this point, i.e., with no electrons inside the diode. The diode starts to integrate when all electrons are evacuated from the PPD (start-of-integration event). The diode voltage in this stage is defined accurately to the same value for each event. This enables noise reduction and it is the main advantage of the fully pinned PD over conventional diodes.
In order to insure low noise operation, all electrons must be evacuated from the diode through the link region between the diode and the transfer gate MX. The link between pinned photodiode and transfer gate MX is very sensitive to variations in the fabrication process tolerances associated with the semiconductor fabrication facility used to make the CMOS image sensor “chips” that includes CMOS image sensor pixels, such as the 4T CMOS image sensor pixel with a fully pinned photodiodes of FIG. 1. Thus, it is important that the fabrication process utilized to produce image sensors including fully pinned photodiodes reliably link the fully pinned photodiodes to their associated transfer gate.
Prior Art 1
One approach for addressing the photodiode/transfer gate linking problem is implemented by forming the diode diffusion region adjacent to the transfer gate using a self-aligned shallow implantation process. This solution is used when the alignment tolerances of a particular fabrication facility are relatively inaccurate, and is depicted in FIGS. 2(A) to 2(D).
Referring to FIG. 2(A), a thermal oxide layer 51 is created on a p-type silicon wafer 50, followed by a polycrystalline silicon (polysilicon) layer 52, and finally a 1st photoresist layer 53. As indicated in FIG. 2(B), the photoresist is exposed and developed to create a transfer gate mask 54. In FIG. 2(C) the polysilicon layer is then etched using the transfer gate mask to form a polysilicon transfer gate 55, and the transfer gate mask is then removed. As shown in FIG. 2(C), a 2nd photoresist layer 56 is patterned to expose the silicon wafer on one side of transfer gate 55, and to protect the rest of silicon wafer 50. Finally, as shown in FIG. 2(D), a diode implant process is performed in which ions are bombarded at an angle (as indicated by arrows). As a result, if the energy of the bombardment ions is low enough, bombardment ions do not penetrate the Silicon wafer area below the transfer gate 55 except at the left edge, which is not protected by photoresist. In this way the conducting implant region 50A has a fixed overlap with the MOS gate edge. Subsequently, a third mask (not shown) is formed over the implant region, and a transfer gate drain region is formed on the right side of the transfer gate poly using known CMOS fabrication techniques.
A problem associated with the above approach is that the resulting implant region 50A is relatively shallow (100 to 300 nm, depends on the thickness of the TG poly, and the microstructure of the polysilicon), and is thus insufficient to provide a suitable photodiode in some applications.
Prior Art 2
A second approach for addressing the photodiode/transfer gate linking problem involves forming a shallow implant that is self aligned to the polysilicon gate and its photoresist. This solution is depicted in FIGS. 3(A) to 3(D).
Similar to the process described above with FIGS. 2(A) and 2(B), FIG. 3(A) shows a thin thermal oxide layer 51 created on a p-type silicon wafer 50, followed by a polysilicon layer 52, and a 1st photoresist layer 53 having a standard mask thickness, and FIG. 3(B) shows a patterned portion of the first photoresist forming a transfer gate mask 54 on polysilicon layer 52. In FIG. 3(C) the polysilicon layer is then etched as above using transfer gate mask 54 to form a polysilicon transfer gate 55, but in this case transfer gate mask 54 is retained. Then a 2nd photoresist layer 60 is patterned over transfer gate mask 54 such that silicon wafer 50 is exposed on one side of the transfer gate 55, and the rest of the silicon wafer is masked. Finally, as shown in FIG. 3(D), a diode implant process is performed. In this way, the stop layer for ion implantation on the polysilicon gate (i.e., provided by the retained transfer gate mask 54) is thicker than in the approach described above, thus allowing a higher energy implant process that produces an implant region 50B having a depth of up to 600 nm, depending on the thickness of the polysilicon making up transfer gate 55, the microstructure of the polysilicon, and on the thickness of retained transfer gate mask 54 (after the etch process). However in advanced semiconductor fabrication, such as 0.25 um technology and below, due to the polysilicon thickness and the retained photoresist, the resulting implant region 50B is still too shallow to provide a suitable photodiode in some applications.
Prior Art 3
A third approach to addressing the photodiode/transfer gate linking problem is to form the diode diffusion region prior to forming the polysilicon transfer gate. This solution is used where the alignment tolerances of a particular fabrication facility are relatively accurate, and is depicted in FIGS. 4(A) to 4(C).
FIG. 4(A) shows a thermal oxide layer 51 created on a p-type silicon wafer 50, followed by a thick photoresist layer 62, which is patterned as shown in FIG. 4(B) to form a thick mask 64. As indicated in FIG. 4(C), due to the relatively thick photoresist layer forming mask 64, a relatively heavy implant can be performed to form a deep implant region SOC having a depth of 800 to 2500 nm. As shown in FIG. 4(D), the mask is then removed, and a polysilicon transfer gate 55 is then formed using the process described above.
The non-self-aligned approach described above provides a good solution to implanting high energy implant into the substrate. However, the method presents a new problem in that, unlike in the ideal case shown in FIG. 4(D), the polysilicon edge and the implant edge are touching, process tolerance variations of a given fabrication facility typically result in separation of these structures. FIG. 5(A) shows a first practical case where a spacing S is defined by between the implant and the polysilicon gate, and FIG. 5(B) shows a second practical case where the polysilicon gate overlaps the edge of the implant (indicated by dashed line circle), which is also undesirable.
Thus, none of the approaches described above produce a suitable CMOS image sensor with pinned photodiode. The first and second “self-aligned” prior art approaches provide a high level of certainty of proper alignment between the implant and gate, but cannot be used to produce an implant having a sufficient depth. Conversely, the third approach provides an implant having a suitable depth, but does not provide certainty of proper alignment between the implant and gate.
Thus, what is needed is a method for fabricating ICs with deep implant regions that are reliably aligned with a corresponding polysilicon gate structure. For example, what is needed is a method for fabricating a CMOS image sensor with pinned photodiode that both facilitates an implant region having a suitable depth, and provides certainty of proper alignment between the implant and gate.